STRUCTURE AND METHOD FOR MANUFACTURING PLANAR STRAINED Si/SiGe SUBSTRATE WITH MULTIPLE ORIENTATIONS AND DIFFERENT STRESS LEVELS

ABSTRACT

The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. Ser. No.10/905,978, filed Jan. 28, 2005, which is related to co-assigned U.S.patent application Ser. No. 10/250,241 entitled HIGH PERFORMANCE SOIDEVICES ON HYBRID CRYSTAL-ORIENTATED SUBSTRATES, filed Jun. 17, 2003,now U.S. Patent Application Publication No. 2004-0256700, andco-assigned U.S. patent application Ser. No. 10/710,277 entitledSTRUCTURE AND METHOD FOR MANUFACTURING PLANAR SOI SUBSTRATE WITHMULTIPLE ORIENTATIONS, filed Jun. 30, 2004, now U.S. Pat. No. 7,094,634,the entire content and subject matter of which are incorporated hereinby reference.

FIELD OF THE INVENTION

The present invention relates to semiconductor materials having enhancedelectron and hole mobilities, and more particularly, to semiconductormaterials that include a silicon (Si)-containing layer having enhancedelectron and hole mobilities. The present invention also providesmethods for forming such semiconductor materials.

BACKGROUND OF THE INVENTION

For more than three decades, the continued miniaturization of siliconmetal oxide semiconductor field effect transistors (MOSFETs) has driventhe worldwide semiconductor industry. Various showstoppers to continuedscaling have been predicated for decades, but a history of innovationhas sustained Moore's Law in spite of many challenges. However, thereare growing signs today that metal oxide semiconductor transistors arebeginning to reach their traditional scaling limits. A concise summaryof near-term and long-term challenges to continued CMOS scaling can befound in the “Grand Challenges” section of the 2002 Update of theInternational Technology Roadmap for Semiconductors (ITRS). A verythorough review of the device, material, circuit, and systems can befound in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issuededicated to the limits of semiconductor technology.

Since it has become increasingly difficult to improve MOSFETs andtherefore complementary metal oxide semiconductor (CMOS) performancethrough continued scaling, methods for improving performance withoutscaling have become critical. One approach for doing this is to increasecarrier (electron and/or hole) mobilities. This can be done by either:(1) introducing the appropriate strain into the Si lattice; (2) bybuilding MOSFETs on Si surfaces that are orientated in directionsdifferent than the conventional <100> Si; or (3) a combination of (1)and (2).

As far as approach (1) is concerned, the application of stresses orstrains changes the lattice dimensions of the Si-containing layer. Bychanging the lattice dimensions, the energy band gap of the material ischanged as well. The change may only be slight in intrinsicsemiconductors resulting in only a small change in resistance, but whenthe semiconducting material is doped, i.e., n-type, and partiallyionized, a very small change in the energy bands can cause a largepercentage change in the energy difference between the impurity levelsand the band edge. Thus, the change in resistance of the material withstress is large.

Prior attempts to provide strain-based improvements of semiconductorsubstrates have utilized etch stop liners or embedded SiGe structures.N-type channel field effect transistors (nFETs) need tension on thechannel for strain-based device improvements, while p-type channel fieldeffect transistors (pFETs) need a compressive stress on the channel forstrain-based device improvements.

In terms of approach (2), electrons are known to have a high mobilityfor a (100) Si surface orientation, but holes are known to have highmobility for a (110) surface orientation. That is, hole mobility valueson (100) Si are roughly 2×-4× lower than the corresponding electronmobility for this crystallographic orientation. To compensate for thisdiscrepancy, pFETs are typically designed with larger widths in order tobalance pull-up currents against the nFET pull-down currents and achieveuniform circuit switching. NFETs having larger widths are undesirablesince they take up a significant amount of chip area.

On the other hand, hole mobilities on the (110) crystal plane of Si areapproximately 2× higher than on the (100) crystal plane of Si;therefore, pFETs formed on a surface having a (100) crystal plane willexhibit significantly higher drive currents than pFETs formed on asurface having a (100) crystal plane. Unfortunately, electron Nobilitieson the (110) crystal plane of Si are significantly degraded compared tothe (100) crystal plane of Si.

There is interest in integrating strained substrates having multiplecrystallographic orientations with silicon-on-insulator (SOI)technology. SOI substrates reduce parasitic capacitance within theintegrated circuit, reduce individual circuit loads and reduce theincidence of latch-up, thereby improving circuit and chip performance.

In view of the state of the art mentioned above, there is a continuedneed for providing a strained Si/SiGe on insulator substrate withmultiple crystallographic orientations and different stress levels.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a multiplecrystallographic orientation strained Si/SiGe-on-insulator (SGOI)substrate.

Another object of the present invention is to provide a SGOI substratethat integrates strained silicon nFETs on a (100) crystal plane withstrained silicon pFETs on a (110) crystal plane.

These and other objects and advantages are achieved in the presentinvention by utilizing a method that provides a multiple orientationstrained SCOI substrate including bonding, masking, etching andepitaxial regrowth process steps. Specifically, the method of thepresent invention comprises the steps of

providing an initial structure having a first device region and a seconddevice region positioned on and separated by an insulating material,said first device region comprising a first orientation material andsaid second device region comprising an insulating layer atop a secondorientation material, wherein said first orientation material and saidsecond orientation material have different crystallographicorientations;

forming a first concentration of lattice modifying material atop saidfirst orientation material;

forming a protective layer atop said first concentration of latticemodifying material;

removing said insulating layer atop said second orientation material;

forming a second concentration of said lattice modifying material atopsaid second orientation material;

removing said protective layer from said first concentration of latticemodifying material;

intermixing said first concentration of lattice modifying material withsaid first orientation material to produce a first lattice dimensionsurface and said second concentration of lattice modifying material withsaid second orientation material to produce a second lattice dimensionsurface; and

forming a first strained semiconducting layer atop said first latticedimension surface and a second strained semiconducting layer atop saidsecond lattice dimension surface, said first strained semiconductinglayer having a same or a different internal stress than said secondsemiconducting layer, said second strained semiconducting layer having adifferent crystallographic orientation than the first semiconductinglayer.

In accordance with the present invention, the lattice modifying materialmay comprise SiGe. Increasing the Ge concentration in the latticemodifying material, increases the strain produced in the subsequentlyformed first strained semiconducting layer and second strainedsemiconducting layer. The concentration of Ge present in the latticemodifying material atop the first device region and the second deviceregion can be controlled using deposition, photolithography and etching.

A first concentration of lattice modifying material is epitaxially grownatop the first orientation material in the first device region.Epitaxial growth requires a crystalline silicon-containing surface;therefore the first concentration of lattice modifying material does notgrow atop the insulating layer in the second device region. A protectivelayer is then blanket deposited atop at least the first device regionand the second device region. A protective mask is then formed atop aportion of the protective liner that is positioned on the firstconcentration of lattice modifying material in the first device region.The protective layer and the insulating layer are then removed from thesecond device region to expose the second orientation material,

Once the second orientation material is exposed, the secondconcentration of lattice modifying material is epitaxially grown atopthe second orientation material in the second device region, while theremaining portion of the protective layer ensures that epitaxial growthdoes not occur in the first device region. Thereafter, the remainingportion of the protective layer is removed.

In a next process step, thermal processing of the structure in anoxidizing environment causes intermixing between the lattice modifyingmaterials and the underlying first orientation material and secondorientation material to produce a first lattice dimension surface andsecond lattice dimension surface capped with an oxidation layer.

Following the removal of the oxidation layer, a first strainedsemiconducting layer can be formed atop the first lattice dimensionsurface and a second strained semiconducting material can be formed atopthe second orientation material. The Ge concentration and thecrystallographic orientation in the first and second strainedsemiconducting layers may be independently selected to provide optimizeddevice regions for both pFET or nFFT devices.

In another embodiment of the present invention, a method is provided forproducing a multiple orientation strained Si/SiGe-on-insulator (SGOI)substrate in which the initial structure utilized in the method does notinclude an insulating layer atop the second orientation material withinthe second device region as disclosed above. Broadly, the inventivemethod comprises:

providing an initial structure having a first device region and a seconddevice region positioned on and separated by an insulating material,said first device region comprising a first orientation material andsaid second device region comprises a second orientation material,wherein said first orientation material and said second orientationmaterial have different crystallographic orientations;

forming a protective layer atop said second orientation material;

forming a first concentration of lattice modifying material atop thefirst orientation material;

removing said protective layer to expose said second orientationmaterial;

forming a protective liner atop said first concentration of latticemodifying material;

forming a second concentration of said lattice modifying material atopsaid second orientation material;

intermixing said first concentration of lattice modifying material withsaid first orientation material to produce a first lattice dimensionsurface and said second concentration of lattice modifying material withsaid second orientation material to produce a second lattice dimensionsurface; and

forming a first strained semiconducting layer atop said first latticedimension surface and a second strained semiconducting layer atop saidsecond lattice dimension surface, said first strained semiconductinglayer having a same or a different internal stress than said secondsemiconducting layer, said second strained semiconducting layer havingsaid different crystallographic orientation than said first strainedsemiconducting layer.

Another aspect of the present invention is an inventive multipleorientation strained Si/SiGe-on-insulator (SGOI) substrate formed by theabove methods. Broadly the inventive structure comprises:

an insulating layer atop a substrate;

an SOI layer atop the insulating layer, the SOI layer comprising a firstlattice dimension material and a second lattice dimension materialseparated by an insulating material, wherein the first lattice dimensionmaterial has a lattice constant different than the second latticedimension material;

a first strained semiconducting layer atop the first lattice dimensionmaterial, the first strained semiconducting material having a firstcrystallographic orientation; and

a second strained semiconducting layer atop the second lattice dimensionmaterial, the second strained semiconducting material having a secondcrystallographic orientation different from the first crystallographicorientation.

In accordance with the present invention, the first strainedsemiconducting layer further comprises at least one pFET device and thesecond strained semiconducting layer further comprises at least one nFETdevice, when the first crystallographic orientation has a (110) crystalplane, the second crystallographic orientation has a (100) crystal planeand the first strained semiconducting layer has a higher internal stressthan the second strained semiconducting layer. In another embodiment ofthe present invention, the lattice constant of the first latticedimension material may be the same as the lattice constant of the secondlattice dimension material.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-10 are pictorial representations (through cross sectional views)illustrating the basic processing steps utilized in one embodiment ofthe present invention to form a strained SGOI substrate having multiplecrystallographic orientation planes.

FIGS. 11-19 are pictorial representations (through cross sectionalviews) illustrating the basic processing steps utilized in anotherembodiment of the present invention to form a substantially planar SGOIsubstrate having a strained SGOI layer having multiple crystallographicorientation planes.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a method of forming a SGOIsubstrate having different crystallographic surfaces, will now bedescribed in greater detail by referring to the following discussion aswell as the drawings that accompany the present application. In theaccompanying drawings, like and correspondence elements are referred toby like reference numerals.

The first embodiment of the present invention is now described withreference to FIGS. 1-11. This embodiment provides a strained SGOIsubstrate comprising device regions separated by insulating material, inwhich each device region has a crystallographic orientation and internalstress that is optimized for a specific type of semiconducting device.For example, the following method can provide a first device regionhaving a crystallographic orientation and internal stress that isoptimized for pFET devices and a second device region having acrystallographic orientation and internal stress that is optimized fornFET devices.

Reference is first made to the initial structure shown in FIG. 1, inwhich a bonded substrate 10, i.e., hybrid substrate, is provided. Asshown, bonded substrate 10 includes a first semiconductor layer 16, afirst insulating layer 14, and a second semiconductor layer 12. Thebonded substrate 10 may be formed using conventional thermal bondingmethods.

The first semiconductor layer 16 is comprised of any semiconductingmaterial including, for example, Si, SiC, SiGe, SiGeC, Ge alloys, GaAs,InAs, InP as well as other III/V or II/VI compound semiconductors. Firstsemiconductor layer 16 may also comprise an SOI layer of a preformed SOTsubstrate or a layered semiconductor such as, for example, Si/SiGe. Thefirst semiconductor layer 16 has a first crystallographic orientation,preferably having a (100) crystal plane. Although a (100) crystal planeis preferred, the first semiconductor layer 16 may alternatively have afirst crystallographic orientation having a (111) crystal plane, a (110)crystal plane or other crystal planes.

The thickness of the first semiconductor layer 16 may vary depending onthe initial starting wafers used to form the bonded substrate 10.Typically, however, the first semiconductor layer 16 has a thicknessfrom about 5 nm to about 500 nm, with a thickness from about 5 nm toabout 100 nm being more highly preferred.

The first insulating layer 14 which is located between the firstsemiconductor layer 16 and the second semiconductor layer 12 has avariable thickness depending upon the initial wafers used to create thebonded substrate 10. Typically, however, the first insulating layer 14has a thickness from about 10 nm to about 500 nm, with a thickness fromabout 20 nm to about 100 nm being more highly preferred. The firstinsulating layer 14 is a nitride, oxide or other like insulatormaterial, preferably a nitride, such as Si₃N₄.

The second semiconductor layer 12 is comprised of any semiconductingmaterial which may be the same or different from that of the firstsemiconductor layer 16. Thus, second semiconductor layer 12 may include,for example, Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP as well asother IIl/V or II/VI compound semiconductors. Second semiconductor layer12 may also comprise an SOI layer of a preformed SOI substrate or alayered semiconductor such as, for example, Si/SiGe. The secondsemiconductor layer 12 has a second crystallographic orientation, whichis different from the first crystallographic orientation. Since thefirst semiconductor layer 16 is preferably a surface having a (100)crystal plane, the second semiconductor layer 12 preferably has acrystallographic orientation having a (110) crystal plane or othercrystal planes. Although the second crystallographic orientation of thesecond semiconductor layer 12 preferably has a (110) crystal plane, thesecond semiconducting layer 12 may alternatively have a (111) crystalplane, a (100) crystal plane or other crystal planes.

In a first process step, an etch mask is formed on a predeterminedportion of the first semiconductor layer 16, so as to protect a portionof the bonded substrate 10, while leaving another portion of the bondedsubstrate 10 unprotected. The etch mask may comprise a photoresist or bea single or multi-layer dielectric hardmask. The unprotected portion ofthe bonded substrate 10 defines a first device area 24 of the structure,whereas the protected portion of the bonded substrate 10 defines asecond device region 22. After providing the etch mask, the structure issubjected to one or more etching steps so as to expose a surface of thesecond semiconductor layer 12. Specifically, the one or more etchingsteps used at this point of the present invention removes theunprotected portions of the first semiconductor layer 16 and theinsulating layer 14, stopping on the second semiconducting layer 12. Theetching used at this point of the present invention may include a dryetching process, such as reactive-ion etching, ion beam etching, plasmaetching or laser etching. The etch mask is then removed.

Insulating material 25 is then formed atop and on the exposed sidewallsof the remaining portions of the first semiconductor layer 16 and thefirst insulating layer 14 in the second device region 22, as depicted inFIG. 2. The insulating material 25 is formed by deposition and etchingand can be comprised of any insulator, such as, for example, an oxide.

Referring to FIG. 3, a semiconductor material 26 is then epitaxiallygrown in the first device region 24, on the exposed surface of thesecond semiconductor layer 12. In accordance with the present invention,semiconductor material 26 has a crystallographic orientation that is thesame as the crystallographic orientation of the second semiconductorlayer 12. Preferably, the crystallographic orientation of the regrownsemiconductor material 26 has a (110) crystal plane. Although a (110)crystal orientation is preferred, the regrown semiconductor material 26may alternatively have a (111), or a (100) crystal plane.

The semiconductor material 26 may comprise any Si-containingsemiconductor, such as Si, strained Si, SiGe, SiC, SiGeC or combinationsthereof, which is capable of being formed utilizing a selectiveepitaxial growth method. In some preferred embodiments, semiconductormaterial 26 is comprised of Si. In the present invention, semiconductormaterial 26 may be referred to as a regrown semiconductor material 26.

In a next process step, a planarization process, such as chemicalmechanical polishing (CMP) or grinding, planarizes the upper surface ofthe regrown semiconductor material 26 to be substantially planar withthe upper surface of the first semiconductor layer 16, as depicted inFIG. 3.

Referring to FIG. 4, in a next process step, a damage interface 28 isformed within the first semiconductor layer 12 by implanting hydrogenions, or other like ions, into the first semiconductor layer 12. Thehydrogen ions may be implanted by conventional ion implantation using adosage ranging from about 1×10¹⁶ atoms/cm² to about 2×10¹⁷ atoms/cm².The hydrogen atoms may be implanted using an implantation energy rangingfrom about 50 keV to about 150 keV.

Following the formation of the damaged interface 28, a planar bondinglayer 33, comprising an insulating layer, is formed on the upper surfaceof the structure depicted in FIG. 3. The planar bonding layer 33 isformed using conventional deposition and planarization. Specifically, aninsulating layer is formed using a conventional deposition process, suchas chemical vapor deposition. The insulating layer is then planarized toproduce the planar bonding layer 33 using a conventional planarizationmethod, such as CMP.

Still referring to FIG. 4, a wafer 30 is then bonded to the planarbonding layer 33. Bonding is achieved by bringing the wafer 30 intointimate contact with the face of the planar bonding layer 33;optionally applying an external force to the contacted wafer 30 andplanar bonding layer 33; and then heating the two contacted surfacesunder conditions that are capable of bonding. The heating step may beperformed in the presence or absence of an external force. Duringbonding, the second semiconductor layer 12 is then separated about thedamaged interface 28 of the second semiconductor layer 12, in which aportion of the second semiconductor layer 12 positioned below thedamaged interface 28 is removed and a portion of the secondsemiconductor layer 12 above the damaged interface 28 remains.

The remaining portion of the second semiconductor layer 12 is thensubjected to a planarization process, such as chemical mechanicalpolishing (CMP) or grinding. The planarization process removes theremaining portion of the second semiconductor layer 12 stopping on thefirst insulating layer 14 and exposing a surface 38 of the regrownsemiconducting material 26. FIG. 5 depicts the resultant structureformed by the above planarization process.

Referring to FIG. 6, in a next process step, a first SiGe layer 34 isgrown atop the exposed surface 38 of the regrown semiconducting material26 in the first device region 24 using a selective epitaxial growthprocess. The first SiGe layer 34 only grows on the exposed surface 38 ofthe regrown semiconducting material 26, since SiGe formed by selectiveepitaxial growth requires a silicon-containing surface. Therefore, sincethe exposed surface of the second device region 22 is the firstinsulating layer 14, the first SiGe layer 34 does not grow within thesecond device region 22.

Preferably, the first SiGe layer 34 is grown having a first Geconcentration ranging from about 20 atomic number % to about 40 atomicnumber %, where the concentration of Ge is selected to produce theappropriate stress within the subsequently formed first strainedsemiconducting layer for a pFET device. Alternatively, the SiGe layer 34is grown having a first Ge concentration ranging about 5 atomic number %to about 30 atomic number %, where the concentration of Ge is selectedto produce the appropriate strain within the subsequently formed firststrained semiconducting layer for an pFET device. Alternatively, the Geconcentration may range from 0 atomic number % to 100 atomic number %.The first SiGe layer 34 may also be referred to as the firstconcentration of lattice modifying material.

Still referring to FIG. 6, a protective layer 35 is then formed atop thefirst device region 24, including the first SiGe layer 34, and thesecond device region 22. The protective layer 35 comprises an insulatingmaterial, preferably a nitride such as Si₃N₄. The protective layer 35may be formed using deposition methods including, but not limited to:chemical vapor deposition (CVD), low-pressure chemical vapor deposition(LPCVD), plasma enhanced chemical vapor deposition (PECVD) or rapidthermal chemical vapor deposition (RTCVD). The protective layer 35 mayhave a thickness ranging from about 10 nm to about 20 nm.

Following the formation of the protective layer 35, a photoresist blockmask 36 is formed overlying at least the first SiGe layer 34. Thephotoresist block mask 36 may be formed by conventional deposition andphotolithography. For example, a layer of photoresist may be blanketdeposited atop the surface of the entire structure including the firstand second device regions 24, 22. The layer of photoresist is thenpatterned using conventional photolithography. Specifically, the layerof photoresist is patterned by exposing the photoresist layer to apattern of radiation and then developing the pattern into thephotoresist utilizing a conventional resist developer. Once thepatterning of the photoresist layer is completed, the second deviceregion 22 is exposed, while the photoresist block mask 36 protects thefirst device region 24.

Following the formation of the photoresist block mask 36, the protectivelayer 35 and the insulating layer 14 are removed from the second deviceregion 22 to expose the first semiconductor layer 16. Preferably, theinsulating layer 14 and the protective layer 35 are removed from thesecond device region 22 by a directional etch process, such as reactiveion etch, having high selectivity to removing the insulating layer 14and protective layer 35, without substantially etching the insulatingmaterial 25, the photoresist block mask 36, and the first semiconductorlayer 16.

Referring to FIG. 7, in a next process step, a second SiGe layer 37 isgrown atop the first semiconductor layer 16 in the second device region22 using a selective epitaxial growth process. The second SiGe layer 37only grows on the surface of the first semiconductor layer 16, sinceepitaxially growth SiGe requires a silicon-containing surface.Therefore, since the protective layer 35 is positioned atop the firstdevice region 24, the second SiGe layer 37 will not grow within thefirst device region 24.

Preferably, the second SiGe layer 37 is grown having a second Geconcentration ranging from about 5% to about 30%, where theconcentration of Ge is selected to produce the appropriate stress withinthe subsequently formed second strained semiconducting layer for a nFETdevice. Alternatively, the second SiGe layer 37 is grown having a secondGe concentration ranging about 20% to about 40%, where the concentrationof Ge is selected to produce the appropriate stress within thesubsequently formed second strained semiconducting layer for a pFETdevice. In a preferred embodiment, the second Ge concentration in thesecond SiGe layer 37 is different from the first Ge concentration in thefirst SiGe layer 34. Alternatively, the second Ge concentration may bethe same as the first Ge concentration. The second SiGe layer 37 mayalso be referred to as the second concentration of lattice modifyingmaterial.

The structure is then planarized using conventional planarizationprocesses, such as chemical mechanical polishing, stopping on theprotective liner 35. The protective liner 35 is then removed by a highlyselective etch that removes the protective liner 35 withoutsubstantially etching the first SiGe layer 34, the second SiGe layer 37,or the insulating material 25, producing the structure depicted in FIG.7.

Referring to FIG. 8, the structure is then annealed in an oxidizingatmosphere to form a first thermal oxide 39 on the surface of the firstdevice region 24 and a second thermal oxide 40 on the surface of thesecond device region 22. This annealing process may be conducted in anoxidizing atmosphere at a temperature ranging from about 1000° C. toabout 1200° C. for a time period ranging from about 1 hour to 2 hours.Preferably, the first thermal oxide 39 and the second thermal oxide 40comprise SiO₂ and have a thickness ranging from about 30 nm to about 100nm.

During thermal oxidation of the first device region 24 and the seconddevice region 22, the first SiGe layer 34 intermixes with the regrownsemiconductor material 26 to form the first lattice dimension SiGe layer41 and the second SiGe layer 37 intermixes with the first semiconductorlayer 16 to form the second lattice dimension SiGe layer 42. Morespecifically, the first thermal oxide 39 formed atop the first deviceregion 24 drives the Ge from the first SiGe layer 34 into the regrownsemiconducting layer 26 and the second thermal oxide 40 drives the Gefrom the second SiGe layer 37 into the first semiconductor layer 16.

The first lattice dimension SiGe layer 41 preferably has a latticedimension that produces the appropriate strain for nFET deviceimprovements in the subsequently formed first strained semiconductorlayer, which is formed atop the first lattice dimension SiGe layer 41.The second lattice dimension SiGe layer 42 has a lattice dimension thatproduces the appropriate strain in the subsequently formed secondstrained semiconductor layer for optimized performance in pFET devices,in which the subsequently formed second strained semiconductor layer isepitaxially grown atop the second lattice dimension SiGe layer 42. Inthe preferred embodiment, the first lattice dimension SiGe layer 41 hasa different lattice dimension (also referred to as lattice constant)than the second lattice dimension SiGe layer 42. Alternatively, thefirst lattice dimension SiGe layer 41 can have the same latticedimension as the second lattice dimension SiGe layer 42. Thecrystallographic orientation of the regrown semiconductor material 26and the epitaxially grown first SiGe layer 34 is maintained in the firstlattice dimension SiGe layer 41. The crystallographic orientation of thefirst semiconductor layer 16 and the epitaxially grown second SiGe layer37 is maintained in the second lattice dimension SiGe layer 42.

The first thermal oxide 39 and the second thermal oxide 40 are thenremoved using a highly selective etch process to expose the firstlattice dimension SiGe layer 41 and the second lattice dimension SiGelayer 42. Preferably, the highly selective etch process is a timeddirectional etch process, such as reactive ion etch, having a highselectivity for etching the first thermal oxide 39 and the secondthermal oxide 40, without substantially etching the first latticedimension SiGe layer 41 and the second lattice dimension SiGe layer 42.

In one embodiment, an oxide layer may be deposited atop the structureand planarized by conventional planarization methods, such as chemicalmechanical polishing (CMP), prior to the removal of the first thermaloxide 39 and the second thermal oxide 30. In this embodiment, the oxidelayers are also removed by the etch process that exposes the firstlattice dimension SiGe layer 41 and the second lattice dimension SiGelayer 42.

Referring to FIG. 10, in a next process step, a first strainedsemiconducting layer 43 is epitaxially grown atop the first latticedimension SiGe layer 41 and a second strained semiconducting layer 44 isepitaxially grown atop the second lattice dimension SiGe layer 42. Thefirst and second strained semiconducting layers 43, 44 compriseepitaxially formed Si.

The first and second strained semiconducting layer 43, 44 comprise aninternal tensile stress. The internal tensile stress results fromgrowing a material layer, such as the first and second semiconductinglayer 43, 44, having a different lattice dimension than the surface onwhich the material layer is grown, such as the first or second latticedimension SiGe layer 41, 42. An internal tensile stress is producedsince the lattice dimension of the material layer is strained to matchthe lattice dimension of the surface on which the material layer isgrown.

The internal stress produced within the first or second semiconductinglayer 43, 44 is increased by increasing the Ge content in the first orsecond lattice dimensions SiGe layer 41, 42. Silicon has a latticedimension of approximately 5.43 Å, and Ge has a lattice structure on theorder of about 5.65 Å. Therefore, increasing the Ge concentration in thefirst lattice dimension SiGe layer 41 or the second lattice dimensionSiGe layer 42 increases the lattice mismatch between the unstrained Siand the first lattice dimension or second lattice dimension SiGe layer41, 42, which in turn increases the internal stress within theepitaxially grown Si 43, 44. Strain introduced to the device channel canresult in device improvements for both pEET and nFET devices, in whichpFET devices need higher strain levels for device optimization.

The strain produced in the first or second strained semiconducting layer43, 44 is maintained so long as the first or second strainedsemiconducting layer 43, 44 is not grown to a thickness greater than itscritical thickness. Once the first or second strained semiconductinglayer 43, 44 surpasses its critical thickness, relaxation can occur dueto dislocation generation. Relaxation diminishes the internal strainproduced in the deposited layer. The “critical thickness” is the maximumthickness at which the layer will not relax. The thickness of the firststrained semiconducting layer 43 may range from about 5 nm to about 20nm. The thickness of the second strained semiconducting layer 44 mayrange from about 5 nm to about 20 nm.

In a preferred embodiment, the crystallographic orientation of the firstlattice dimension SiGe layer 41 is (110). Although a (110) crystal planeis preferred, the first lattice dimension SiGe layer 41 mayalternatively have a (111), or a (100) crystal plane. Since the firstlattice dimension SiGe layer 41 is preferably in a (110) crystal planesurface, the crystallographic orientation of the second latticedimension SiGe layer 42 is preferably in a (100) crystal plane. Thesecond lattice dimension SiGe layer 42 may alternatively have a (111)crystal plane, a (100) crystal plane or other crystal planes.

Still referring to FIG. 10, the resulting structure comprises an SGOIsubstrate including a first device region 24 having a first strainedsemiconducting layer 43 with a first crystallographic orientation and asecond device region 22 having a second strained semiconducting layer 44with second crystallographic orientation, the first crystallographicorientation being different from the second crystallographicorientation. The internal strain within the first strained semiconductorlayer 43 may be the same or different from the internal strain withinthe second strained semiconductor layer 44.

Preferably, the first strained semiconducting layer 43 has acrystallographic orientation and internal tensile stress for nFET deviceoptimization. More specifically, the first crystallographic orientationis preferably in a (110) crystal plane and the internal tensile stressproduces dislocations that are beneficial to pFET device performance.The second strained semiconducting layer 44 of the second device region22 preferably has a crystallographic orientation and internal stress fornFET device optimization. More specifically, the second crystallographicorientation is preferably in a (100) crystal plane to increase electronmobility and the internal stress avoids dislocation formation thatdegrades nFET device performance.

Still referring to FIG. 10, the SGOI substrate 50 may then be furtherprocessed using conventional MOSFET processing steps to form at leastone pFET device 52 in first device region 24 and at least one nFETdevice 53 in the second device region 22.

Another embodiment of the present invention is now described withreference to FIGS. 11-19. In the previous embodiment depicted in FIGS.1-10, the first strained semiconductor layer 43 can be vertically offsetfrom the second strained semiconductor layer 44 by a vertical dimensionranging from about 50 Å to about 200 Å. The embodiment of the presentinvention depicted in FIGS. 11-19 provides a substantially planarstrained SGOI substrate comprising device regions separated byinsulating material, in which each device region has a crystallographicorientation and internal stress that is optimized for a specific type ofsemiconducting device. Similar to the previous embodiment depicted inFIGS. 1-10, this embodiment of the inventive method can provide a firstdevice region that is optimized for pFET devices and a second deviceregion that is optimized for nFET devices, or alternatively a firstdevice region optimized for nFETs and a second device region optimizedfor pFETs.

Reference is first made to the initial structure shown in FIG. 1. Theinitial structure comprises a bonded substrate 10 similar to thesubstrate depicted FIG. 1 of the previous embodiment, including a firstsemiconductor layer 16, a first insulating layer 14, a secondsemiconductor layer 12, and further comprising a first planarizationstop layer 18. The planarization stop layer 18, which is located betweenthe first insulating layer 14 and the first semiconductor layer 16, hasa thickness ranging from about 5 nm to about 20 nm, with a thickness ofabout 10 nm being highly preferred. The planarization stop layer 18 is anitride or oxynitride material, preferably Si₃N₄.

Similar to the first embodiment, the first semiconductor layer 16 has afirst crystallographic orientation preferably having a (100) crystalplane and the second semiconductor layer 12 has a secondcrystallographic orientation that is preferably a (110) crystal plane.The first semiconductor layer 16 may alternatively have a (111) crystalplane, a (110) crystal plane or other crystal planes and the secondsemiconductor layer 12 may alternatively have a (111) crystal plane, a(100) crystal plane or other crystal planes. In this embodiment, thefirst insulating layer 14 is preferably an oxide, such as SiO₂.

Still referring to FIG. 11, a dielectric stack 5 is then formed atop thefirst semiconductor layer 16. The dielectric stack 5 includes at least asecond insulating layer 6 and a second planarization stop layer 7 andcan be formed using deposition processes well known in the art. Thesecond insulating layer 6 may comprise an oxide, nitride, oxynitride orother insulating material, preferably being SiO₂, and may be formedusing a deposition process, such as, for example, chemical vapordeposition. The second insulating layer 6 can have a thickness fromabout 10 nm to about 500 nm, with a thickness from about 20 nm to about100 nm being more highly preferred.

The second planarization stop layer 7 is a nitride or oxynitridematerial, preferably Si₃N₄, and can be formed using a conventionaldeposition process, such as chemical vapor deposition. The secondplanarization stop layer 7 can have a thickness ranging from about 5 nmto about 20 nm, with a thickness of about 100 nm being highly preferred.

Following the formation of the dielectric stack 5, an etch mask isformed using conventional photoresist deposition and photolithographyprocesses on a predetermined portion of the second insulating layer 6,so as to protect a portion of the dielectric stack 5 and the underlyingbonding substrate 10, while leaving another portion of the dielectricstack 5 and the bonded substrate 10 unprotected. The unprotected portionof the bonded substrate 10 defines a first device area of the structure,whereas the protected portion of the bonded substrate 10 defines asecond device region. After providing the etch mask, the structure issubjected to one or more etching steps, so as to expose a surface of thesecond semiconductor layer 12. The etch mask 20 is then removedutilizing a conventional resist stripping process. Following etch maskremoval, a remaining portion of the second insulating layer 6 is removedusing an etch process having a high selectivity to removing the secondinsulating layer 6, without substantially etching the secondplanarization stop layer 7.

Referring to FIG. 12, an insulating material 25 is then formed atop, andon, the exposed sidewalls of the remaining portions of the secondplanarization stop layer 7, the first semiconductor layer 16, the secondplanarization stop layer 18 and the first insulating layer 14, in thesecond device region 22. The insulating material 25 is similar to theinsulating material 25 of the previous embodiment, as depicted in FIG. 2

In a next process step, a semiconductor material 26 is then epitaxiallygrown in the first device region 24, on the exposed surface of thesecond semiconductor layer 12. In accordance with the present invention,semiconductor material 26 has a crystallographic orientation that is thesame as the crystallographic orientation of the second semiconductorlayer 12. The epitaxially grown semiconductor material 26 is similar tothe regrown semiconductor material 26 of the previous embodiment, whichis described above and depicted in FIG. 3. In the present embodiment,the semiconductor material 26 may be referred to as a regrownsemiconductor material 26, wherein the regrown semiconductor material 26preferably comprises a crystallographic orientation having a (110)crystal plane.

Still referring to FIG. 12, a planarization process, such as chemicalmechanical polishing (CMP) or grinding, is then conducted such that theupper surface of the regrown semiconductor material 26 is substantiallyplanar with the upper surface of the second planarization stop layer 7.A first oxidation layer 27 is then formed atop the semiconductormaterial 26 so that the first device region 24 has a surfacesubstantially coplanar to the second planarization stop layer 7. Thefirst oxidation layer 27 is formed by a thermal oxidation of Si process(local oxidation of silicon (LOCOS)) and can have a thickness rangingfrom about 10 nm to about 15 nm, Similar to the damaged interface 28formed in the previous embodiment and illustrated depicted in FIG. 4, adamaged interface is formed within the second semiconductor layer 12.

In a next process step, the upper surface of the structure depicted inFIG. 12, including the second planarization stop layer 7 and the firstoxidation layer 27, are processed to provide a planar surface for waferbonding. Prior to bonding, the first planarization stop layer 7 can beremoved using a high selectivity etch process, without substantiallyetching the first semiconductor layer 16, insulating material 25, andfirst thermal oxide layer 27.

Referring to FIG. 13, in a next process step, a planar bonding layer 33is formed using deposition and planarization atop the exposed surface ofthe first semiconducting layer 16, the first thermal oxide layer 27, andthe insulating material 25. A wafer 30 is then bonded to the planarbonding layer 33 by conventional thermal bonding. The formation of theplanar bonding layer 33 and bonding the planar bonding layer to thewafer 30 are described in greater detail in the previous embodiment, asdescribed with reference to FIG. 4. The second semiconducting layer 12is then separated about the damaged interface 28, in which a remainingportion 32 of the second semiconducting layer 12 remains, as depicted inFIG. 13.

The remaining portion 32 of the single orientation layer 12 is thensubjected to a planarization process, such as chemical mechanicalpolishing (CMP) or grinding. The planarization process removes theremaining portion 32 of the single orientation layer 12, the firstinsulating layer 14, a portion of the insulating material 25, and aportion of the regrown semiconducting material 26. The planarizationprocess ends on the first planarization stop layer 18.

Referring to FIG. 14, in a next process step, a second thermal oxidelayer 34 is formed atop the exposed surface 38′ of the regrownsemiconducting material 26 so that the regrown semiconducting material26 in the first device region 24 has a surface substantially coplanar tothe first semiconductor layer 6 in the second device region 22. Thesecond thermal oxide layer 34 is formed during by a thermal oxidation ofSi process. The second thermal oxidation consumes Si from the exposedsurface 38′ of the regrown semiconducting material 26, thereforeleveling the upper surface 38′ of the regrown semiconducting material 26in the first device region 24 to the upper surface 37 of the firstsemiconductor layer 16 in the second device region 22. The secondthermal oxide layer 34 can have a thickness ranging from about 10 nm toabout 15 nm, so long as the top surface 38′ of the regrownsemiconducting material 26 is substantially coplanar to the top surface37 of the first semiconductor layer 16. Preferably, the second thermaloxide layer 34 is SiO₂.

Referring to FIG. 15, in a next process step, the second thermal oxidelayer 34 and the first planarization stop layer 18 are removed using aselective etching process, wherein the resulting structure comprises asubstantially planar SOI substrate 51 comprising a first device region24 having a first crystallographic orientation and a second deviceregion 22 having a second crystallographic orientation, the firstcrystallographic orientation being different from the secondcrystallographic orientation. The first device region 24 and the seconddevice region 22 are separated by insulating material 25. Preferably,the first orientation is a (110) crystal plane and the secondorientation is a (100) crystal plane.

Referring to FIG. 16, a protective layer 35 is then formed atop thefirst device region 24 using deposition, photolithography and etching.The protective layer 35 comprises an insulating material, preferably anitride material, such as Si₃N₄. The protective layer 35 may have athickness ranging from about 10 nm to about 20 nm.

Still referring to FIG. 16, in a next process step, a second SiGe layer37 is grown atop the first semiconductor layer 16 in the second deviceregion 22. The second SiGe layer 37 is grown using a selective epitaxialgrowth process similar to the second SiGe layer 34 formed in theprevious embodiment, as described above with reference to FIG. 7. Thesecond SiGe layer 37 is preferably grown having a second Geconcentration selected to produce the appropriate stress for a nFETdevice within the subsequently formed second strained semiconductinglayer. Alternatively, the Ge concentration is selected to produce theappropriate stress for a pFET device within the subsequently formedsecond strained semiconducting layer.

Referring to FIG. 17, the protective layer 35 is then removed by ahighly selective etch that removes the protective liner 35 withoutsubstantially etching the second SiGe layer 37, the first SiGe layer 26,or the insulating material 25. A protective liner 58 is then formed atopthe second device region 22 including the second SiGe layer 37 usingdeposition, photolithography, and etch processes, which are well knownwithin the skill of the art. The protective liner 58 comprises aninsulating material, preferably a nitride material, such as Si₃N₄, andmay have a thickness ranging from about 10 nm to about 20 nm.

In a next process step, the first SiGe layer 34 is grown atop theexposed surface of the regrown semiconducting material 26 in the firstdevice region 24 using a selective epitaxial growth process. The firstSiGe layer 34 is grown using a selective epitaxial growth processsimilar to the first SiGe layer 34 formed in the previous embodiment, asdescribed above with reference to FIG. 7. The first SiGe layer 34 ispreferably grown having a first Ge concentration selected to produce theappropriate stress for a pFET device within the subsequently formedfirst strained semiconducting layer 43. Alternatively, the Geconcentration is selected to produce the appropriate stress for an nFETdevice within the subsequently formed first strained semiconductinglayer 43.

Referring now to FIG. 18, the structure is then annealed to intermix thefirst SiGe layer 34 with the regrown semiconducting material 26 to forma first lattice dimension SiGe layer 41 and to intermix the second SiGelayer 37 with the first semiconductor layer 16 to form a second latticedimension SiGe layer 42. This annealing process is similar to theannealing process of the previous embodiment, described above withreference to FIGS. 8 and 9. To reiterate, an oxidizing atmosphereproduces a first thermal oxide 39 atop the first device region 24 and asecond thermal oxide 40 atop the second device region 22, where theformation of the thermal oxide 39, 40 drives Ge from the first SiGelayer 34 and the second SiGe layer 37 into the regrown semiconductinglayer 26 and the first semiconductor layer 16. The first thermal oxide39 and the second thermal oxide 40 are then removed using highlyselective etch processes to expose the first lattice dimension SiGelayer 41 and the second lattice dimension SiGe layer 42, as depicted inFIG. 18. Due to this high temperature annealing (i.e., 1000° C.-1300°C.), the first lattice dimension SiGe layer 41 and the second latticedimension SiGe layer 42 are relaxed.

The first lattice dimension SiGe layer 41 preferably has a latticedimension that produces the appropriate strain for pFET deviceimprovements in the subsequently formed first strained semiconductorlayer. The second lattice dimension SiGe layer 42 has a latticedimension that produces the appropriate strain in the subsequentlyformed second strained semiconductor layer for optimized performance innFET devices. The first lattice dimension material may be SiGe having aGe concentration ranging from 0.05% to 0.4% and the second latticedimension material may be SiGe having a Ge ranging from about 0.1%concentration to about 0.5%.

The crystallographic orientation of the regrown semiconductor material26 and the epitaxially grown first SiGe layer 34 is maintained in thefirst lattice dimension SiGe layer 41. The crystallographic orientationof the first semiconductor layer 16 and the epitaxially grown secondSiGe layer 37 is maintained in the second lattice dimension SiGe layer42.

Referring to FIG. 19, in a next process step, a first strainedsemiconducting layer 43 is epitaxially grown atop the first latticedimension SiGe layer 41 and a second strained semiconducting layer 44 isepitaxially grown atop the second lattice dimension SiGe layer 42. Thefirst and second strained semiconducting layers 43, 44 compriseepitaxially formed Si.

Similar to the previous embodiment, the first and second strainedsemiconducting layers 43, 44 comprise an internal tensile stress thatresults from the lattice mismatch between the smaller lattice dimensionof epitaxially grown Si of the first and second semiconducting layers43, 44 being formed atop the larger lattice dimension of the first andsecond lattice dimension SiGe layer 41, 42.

Preferably, the lattice mismatch between unstrained semiconducting layer43 and the first lattice dimension SiGe layer 41 increases pFET deviceimprovements and the lattice mismatch between the unstrainedsemiconducting layer 44 and the second lattice dimension SiGe layer 41does not degrade nFET performance. The strain produced in the first orsecond strained semiconducting layer 43, 44 is maintained so long as thefirst or second strained semiconducting layer 43, 44 is not grown to athickness greater than its critical thickness.

In a preferred embodiment, the crystallographic orientation of the firstlattice dimension SiGe layer 41 is (110). Although a (110) crystal planeis preferred, the first lattice dimension SiGe layer 41 mayalternatively have a (111) or a (100) crystal plane. Since the firstlattice dimension SiGe layer 41 is preferably in a (110) crystal plane,the crystallographic orientation of the second lattice dimension SiGelayer 42 is preferably in a (100) crystal plane. Although a (100)crystal plane is preferred, the second lattice dimension SiGe layer 42may alternatively have a (111) or a (110) crystal plane.

Still referring to FIG. 19, the resulting structure comprises asubstantially planar SOI substrate including a first device region 24having a first strained semiconducting layer 43 with a firstcrystallographic orientation and a second device region 22 having asecond strained semiconducting layer 44 with a second crystallographicorientation, the first crystallographic orientation being different fromthe second crystallographic orientation. Preferably, the first strainedsemiconducting layer 43 has a crystallographic orientation and internaltensile stress for pFET device optimization. The second strainedsemiconducting layer 44 of the second device region 22, preferably has acrystallographic orientation and internal stress for nFET deviceoptimization. The substantially planar substrate 51 may then be furtherprocessed using conventional MOSFET processing steps to form at leastone pFET device 52 in first device region 24 and at least one nFETdevice 53 in the second device region 22.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made with departing from the spirit and scope of thepresent invention. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustrated,but fall within the scope of the appended claims.

1. A substrate comprising: an insulating layer; an SOI layer atop saidinsulating layer, said SOI layer comprising a first lattice dimensionmaterial and a second lattice dimension material separated by aninsulating material; a first strained semiconducting layer atop saidfirst lattice dimension material, said first strained semiconductingmaterial having a first crystallographic orientation; and a secondstrained semiconducting layer atop said second lattice dimensionmaterial, said second strained semiconducting material having a secondcrystallographic orientation different from said first crystallographicorientation.
 2. The semiconductor substrate of claim 1, wherein saidfirst crystallographic orientation is in a (110) crystal plane and saidsecond crystallographic orientation is in a (100) crystal plane.
 3. Thesemiconducting substrate of claim 1 wherein said first lattice dimensionmaterial has a different lattice constant than said second latticedimension material.
 4. The semiconductor substrate of claim 3 whereinsaid first lattice dimension material is SiGe having a Ge fractionranging from about 0.05% to about 0.4% and said second lattice dimensionmaterial is SiGe having a Ge fraction ranging from 0.1% to about 0.5%.5. The semiconducting substrate of claim 1 wherein said first latticedimension material has the same lattice dimension s said second latticedimension material.
 6. The semiconductor substrate of claim 2 wherein atleast one pFET device is positioned on said first strainedsemiconducting layer and at least one nFET device is positioned on saidsecond strained semiconducting layer.
 7. An integrated circuitcomprising: an SOI substrate comprising a pFET semiconducting materialhaving a pFET optimized internal stress and a pFET crystallographicorientation, and an nFET semiconducting material having an nFEToptimized internal stress and an nFET crystallographic orientation,wherein said pFET semiconducting material and said nFET semiconductingmaterial are separated by an insulating material; at least one nFETdevice positioned on said nFET semiconducting material; and at least onepFET device positioned on said pFET semiconducting material.
 8. Theintegrated circuit of claim 7, wherein said first pFET crystallographicorientation is in a (110) crystal plane and said nFET crystallographicorientation is in a (100) crystal plane.